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Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADM1275
VCC 1
UV 2
OV 3
20 SENSE+
19 SENSE–
18 GATE
VCAP 4
ISET 5
SS 6
TIMER 7
ADM1275-1
TOP VIEW
(Not to Scale)
17 GND
16 VOUT
15 FLB
14 PWRGD
OV
VCAP
ISET
SS
TIMER
1
2
3
4
5
PIN 1
INDICATOR
ADM1275-1
TOP VIEW
(Not to Scale)
15 GND
14 VOUT
13 FLB
12 PWRGD
11 SCL
LATCH 8
ADR 9
13 SCL
12 SDA
GPO1/ALERT1/CONV 10
11
GPO2/ALERT2
Figure 3. ADM1275 -1 Pin Configuration, QSOP
NOTES
1. SOLDER THE EXPOSED PADDLE TO
THE BOARD TO IMPROVE THERMAL
DISSIPATION. THE EXPOSED PADDLE
CAN BE CONNECTED TO GROUND.
Figure 4. ADM1275 -1 Pin Configuration, LFCSP
Table 5. ADM1275 -1 Pin Function Descriptions
Pin No.
QSOP
1
LFCSP
19
Mnemonic
VCC
Description
Positive Supply Input Pin. An undervoltage lockout (UVLO) circuit resets the device when a low
supply voltage is detected. GATE is held low when the supply is below UVLO. During normal
operation, this pin should remain greater than or equal to SENSE+ to ensure that specifications
are adhered to. No sequencing is required.
2
20
UV
Undervoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an
internal comparator to detect whether the supply is under the UV limit.
3
4
1
2
OV
VCAP
Overvoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an
internal comparator to detect whether the supply is above the OV limit.
Internal Regulated Supply. A capacitor with a value of 1 μF or greater should be placed on this pin
to maintain good accuracy. This pin can be used as a reference to program the ISET pin voltage.
5
3
ISET
This pin allows the current limit threshold to be programmed. The default limit is set when this pin
is connected directly to VCAP. To achieve a user-defined sense voltage, the current limit can be
adjusted using a resistor divider from VCAP. An external reference can also be used.
6
4
SS
Soft Start Pin. A capacitor is used on this pin to set the soft start ramp profile. The voltage on the
SS pin controls the current sense voltage limit, which controls the inrush current profile.
7
8
9
5
6
7
TIMER
LATCH
ADR
Timer Pin. An external capacitor, C TIMER , sets an initial timing cycle delay and a fault delay. The GATE
pin is pulled low when the voltage on the TIMER pin exceeds the upper threshold.
Signals that the device is latching off after an overcurrent fault. The device can be configured for
automatic retry after latch-off by connecting this pin directly back to the UV pin.
PMBus Address Pin. This pin can be tied to GND, tied to VCAP, left floating, or tied low through a
resistor to set four different PMBus addresses (see the Device Addressing section).
10
8
GPO1/ALERT1/
CONV
General-Purpose Digital Output (GPO1).
Alert (ALERT1). This pin can be configured to generate an alert signal when one or more fault or
warning conditions are detected.
Conversion (CONV). This pin can be used as an input signal to control when a power monitor ADC
sampling cycle begins.
At power-up, this pin defaults to a high impedance state. There is no internal pull-up on this pin.
11
9
GPO2/ALERT2
General-Purpose Digital Output (GPO2).
Alert (ALERT2). This pin can be configured to generate an alert signal when one or more fault or
warning conditions are detected.
At power-up, this pin indicates the FET health mode by default. There is no internal pull-up on this pin.
Rev. D | Page 9 of 48
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